Vigorous research and development is being performed for miniaturization the transistors in a large-scale integrated circuit (LSI) and the thin film transistors (TFTs) in a flat panel display. In a silicon semiconductor process, fine processing down to 0.1 μm or less is realized by reducing the wavelength of a light source for exposure used in a photolithography step. However, there are limits to the miniaturization by a conventional lithography technique. Moreover, with progress in miniaturization, costs of the exposure apparatus and the mask member are rapidly increasing.
In recent years, carbon nanotubes (Non-Patent Document 1) and nanowires which are made of a material exhibiting semiconductor-like properties (Patent Document 1) are drawing attention. Carbon nanotubes and nanowires are nanostructures with a diameter of about 2 nm to 1 μm, which can be formed via self-organization. Therefore, they present a potential of realizing high-performance nanometer-sized electronic devices, without employing any sophisticated lithography technique or etching technique. Such nanostructures are regarded promising as a technique for allowing high-performance devices to be produced at low cost, without employing complicated processing techniques.
Hereinafter, a conventional nanowire structure will be described with reference to FIG. 14.
FIG. 14(a) shows a schematic structural diagram of a nanowire. Generally speaking, a nanowire is a fine columnar structure having a diameter of about 1 nm to 1 μm. The length of this nanowire is about 500 nm to 1 mm, and can be appropriately set according to the application purposes.
FIG. 14(b) shows a nanowire 1002 having a core portion 1003 (inside) and a shell portion 1004 (outside) which are made of different materials (hereinafter referred to as a “core-shell nanowire”)(Patent Document 2).
FIG. 14(c) shows a nanowire 1005 in which a first semiconductor nanowire 1006 and a second semiconductor nanowire 1007 are arranged along the length direction of the nanowire (hetero nanowire)(Patent Document 2).
In a usual hetero growth technique based on epitaxial growth technique, in order to reduce defects and dislocations, the lattice constants must be matched at the hetero interface, which imposes a constraint on the material choices. However, a nanowire having a pseudo one-dimensional structure presents a possibility that the stress due to a lattice constant mismatch can be alleviated, and thus provides an improved freedom of material choices.
Thus, nanowires, which can realize nanostructures and material engineering via self-organization, are considered as promising in the future.    [Patent Document 1] Japanese National Phase PCT Laid-Open Publication No. 2004-535066    [Patent Document 2] Japanese National Phase PCT Laid-Open Publication No. 2004-532133    [Non-Patent Document 1] R. Martel, et al., “Single- and multi carbon nanotube field-effect transistors,” Appl. Phys. Lett. 73 pp. 2447, 1998